Opisy Tematów Seminarium Doktoranckiego INT

Opisy Tematów Seminarium Doktoranckiego INT

Opisy tematów Seminarium doktoranckiego INT:


1. Next-generation ultra-low energy processor logic

This research will address modern challenges faced by energy efficient computing, some of which are:

a) the design and development of novel logic circuits and architectures to obtain extremely low levels of energy consumption while still maintaining performance,
b) generation of energy-aware machine-level software by developing new techniques and algorithms to exploit novel architectures for greater energy efficiency,
c) development of ultra low-energy application-specific processing hardware for selected applications such as digital signal and graphical(image) processing.

These challenges are pertinent primarily to mobile devices (e.g. smartphones, tablet computers) but also to larger-scale systems. Both types of systems require characterisation of the energy efficiency, new modelling and new hardware synthesis techniques where analogue issues and energy-aware machine-code generation are important factors at the hardware design stage.


2. Automated synthesis of mixed-technology systems on chip

This research will develop a methodology for automated synthesis and parametric optimization of mixed-technology analogue Integrated Circuits utilizing the evolutionary optimization approach and machine learning. The versatility of methods developed in the course of this research would allow analogue designers of limited expertise to obtain high performance analogue systems in a multi-stage design process from a specification on a high level of abstraction to a final physical layout implementation. This process currently requires very specific and extensive expertise at different levels and steps throughout the design workflow which nowadays is very rare and very expensive. Methods and tools developed in this PhD will also provide a useful training aid to analogue designers working in applications where continuous improvement is needed, especially for critical high-performance applications. The rapid progress in computational resources, specifically the availability of high-performance, cloud computing resources makes the proposed approach timely as the computational effort and memory requirements necessary to automate complex evolutionary optimisation tasks in a reasonable amount of time are now feasible.


3. Graphene FET Circuit-Level Device Modelling

The graphene material has been widely studied in recent years as it holds promise for the next generation electronic applications. Therefore, there is a need to model its device characteristics. The proposed research will address the state-of the art in the development of dual gate and single gate graphene transistors and will develop circuit levels models for accurate simulation and optimisation of graphene and mixed, graphene-silicon devices. Particular attention will be given to 3D multi-later graphene structures and the development of partial differential equations for such models, their integration with SPICE-like circuit-level simulators and performance optimisation.